The present invention concerns the control of invertors, and relates more particularly the control of three-phase or multi-three-phase invertors.
In order to control a three-phase motor efficiently, it is necessary to use a control algorithm which employs three-phase currents.
In most invertor systems, information relating to the phase currents is necessary.
A first known method of obtaining these currents consists in detecting them directly, but this needs at least two sensors applied directly to the phases of the motor, depending on the connections of the windings of the motor. These types of sensors are usually expensive because of their sophisticated nature and the need to isolate them.
Another way which is also known is to detect only the line current and measure the three phase currents on the basis of this line current. This second method needs a simple inexpensive resistor as sensor and does not need to be isolated.
Since the switching state of the invertor is controlled directly, using a digital signal processor, it is possible to ascertain the exact electrical path taken by the input current through the invertor to each phase.
The phase currents can then be linked directly with the line currents. The phase currents which are obtained are due to an actual detection of the current, and are not the result of a simulation which needs a model of the output circuit. The means of estimation is therefore fully independent of the input and output circuits of the invertor.
The phase currents are estimated on the basis of the line direct current, as a function of the state of the invertor.
Under certain conditions, the time difference between two states of the invertor is very small. In this case, because of the switching time of the transistors involved in the construction of the invertor, the presence of a dead band, and the response delays of the electronic processing circuits the phase signal is invisible on the line current which is processed. As a consequence, no current measurement is possible during this period.
A known method gives a solution for overcoming this limitation due to the circuit and for making an estimate of the current with better precision in a wider range of loads and speeds than the methods described above allow.
An invertor generally includes three pairs of switching elements, for example transistors, the emitter-collector paths of the transistors in each pair being connected in series to the terminals of a DC voltage source.
The bases of the transistors of each pair are connected to the pulse-width-modulation control outputs of a processor and respectively receive a switching signal and its complement. The connections between the transistors in each pair are each connected to a phase winding of the motor to be controlled.
The following situation will be considered. In order to represent the switching state of an invertor, a switching function Sa is defined for a phase A as follows: Sa=1 when the upper transistor of the phase A is on, and Sa=0 when the lower transistor of the phase A is on, and the upper transistor is off.
Similar definitions can be given for the phases B and C.
The signals Sa, Sb, Sc controlling the lower transistors are the opposites of the signals Sa, Sb, Sc with a dead band being added.
The term dead band is used to denote the time difference between the switching of the upper and lower transistors of the same phase. The two transistors of each phase are never on at the same time. The purpose of the dead band is to protect the energy devices supplied by the invertor during the switching, by avoiding on-state overlaps and consequently high transient currents.
The stator current can then be expressed as a function of the switching states of the transistors of the invertor,
idc=ia when (Sa, Sb, Sc)=(1,0,0) PA1 idc=-ia when (Sa, Sb, Sc)=(0,1,1) PA1 idc=ib when (Sa, Sb, Sc)=(0,1,0) PA1 idc=-ib when (Sa, Sb, Sc)=(1,0,1) PA1 idc=ic when (Sa, Sb, Sc)=(0,0,1) PA1 idc=-ic when (Sa, Sb, Sc)=(1,1,0) PA1 idc=0 when (Sa, Sb, Sc)=(1,1,1) PA1 idc=0 when (Sa, Sb, Sc)=(0,0,0) PA1 (n-1) compensation U1+measurement U1=n U1 PA1 (n-1) compensation U2+measurement U2=n U2 in which n is the integer number of pulse-width-modulation periods per slaving cycle. PA1 (n-1) compensation U1+measurement U1=n U1 PA1 (n-1) compensation U2+measurement U2=n U2 in which n is the integer number of pulse-width-modulation periods per slaving cycle.
By using the equations mentioned above as a basis, a phase current can be related to the DC line current. In consequence, three phase currents can be measured by considering only the line in direct current.
If the pulse-width-modulation frequency is high enough, the phase current changes only slightly over one or two pulse-width-modulation periods. A measured phase current thus gives a reasonable approximation of the true current.
For example, when an interrupt 1 takes place, the state of the invertor is (0,0,1) and the phase current measured is ic=idc. After interrupt 2, the sample current will be determined by (1,0,1), so that ib=-idc.
One way of phase current reconstruction consists in generating a configuration for a control cycle time lasting 250 .mu.s, for example. The line current is then sampled every 15.6 .mu.s and sorted according to the switching state to update a stack containing the estimated phase current. With the samples obtained, an average is processed to determine each estimated phase current.
Given that the sampling takes place with fixed time, some small configurations, less than 30 .mu.s, may be undetected. In order to remedy these undetectable signals, a zero duty cycle will be used for the first pulse-width modulation and the theoretical pulse-width modulation will be accumulated for the duty cycle of the following period of the same vector. This process continues until the accumulated duty cycle exceeds 30 .mu.s.
Given that the samples are not synchronized with the states of the invertor, a large minimum duty cycle (here 30 .mu.s) is needed in order to make the line current coincide with the appropriate state.
Let U1 be the time interval between the switching of a transistor of a first phase, from the start of a pulse-width-modulation period, and the switching of a corresponding transistor of a following phase.
Let U2 be the time interval between the instant of switching of a transistor of the following phase and the switching of the corresponding transistor of the remaining phase.
Under certain conditions, U1 or U2 are very small and, because of the switching time of the transistors, the presence of a dead band and response delays of the electronic processing circuits, the phase signal is invisible in the line current.